18 Mbit NoBL synchronous SRAM — 133 MHz, 6.5 ns access
The part is volatile, SDR (single data rate), and comes in a 100-pin LQFP package (14x20 mm body).
Obsolete — plan your BOM transition
For new designs or a long-term production fix, you will need a drop-in or functionally equivalent replacement. A cross-reference search against the 100-pin TQFP footprint, 3.3 V supply, and 133 MHz speed grade is the practical next step.
The 133 MHz clock rate and 6.5 ns access time define the part's place in a high-speed synchronous memory bus. A 133 MHz clock period is about 7.5 ns, so the 6.5 ns access leaves roughly 1 ns of setup margin before the next rising edge — tight but workable with proper PCB layout (matched trace lengths, controlled impedance, and adequate decoupling on the 3.3 V rail). The NoBL architecture eliminates the dead bus cycle between reads and writes, giving back-to-back throughput at the full clock rate. This matters for applications like packet buffering or cache tag RAM where every cycle counts.
Package and footprint: 100-TQFP (14x20 mm)
It is a surface-mount, RoHS-compatible package (the 'I' suffix indicates industrial temperature and lead-free). The footprint is standard for 100-pin TQFPs of this body size; verify the land pattern against the mechanical drawing in the datasheet.