Part identity and key parametrics
The Infineon CY7C1361C-100BGC is a 9Mbit synchronous SDR SRAM organized as 256K x 36 bits, clocked at 100 MHz with an 8.5 ns access time. This is a pipelined synchronous SRAM intended for high-throughput applications such as network switch buffers, telecom line cards, and cache memory in embedded systems where deterministic read/write latency at 100 MHz is required.
Timing and bus interface
The 100 MHz clock and 8.5 ns access time define the window for address-to-data valid after clock edge.
The 119-PBGA (14x22 mm) package is a fine-pitch BGA. Reflow profile must follow the JEDEC moisture sensitivity level for the specific date code lot.
Infineon lists the CY7C1361C-100BGC as Obsolete. This means the manufacturer has ceased production and no further last-time-buy windows are open.