9 Mbit synchronous SRAM for high-throughput data buffering
The Infineon CY7C1360C-166AJXCT is a 9 Mbit synchronous SRAM organised as 256K x 36 bits, clocked at 166 MHz with a 3.5 ns access time. As an SDR (Single Data Rate) synchronous SRAM, it latches addresses and data on the rising clock edge, making it a fit for networking buffers, cache memory, and DSP pipelines where deterministic read/write timing matters.
166 MHz clock and 3.5 ns access — what they mean for the bus
The 166 MHz clock frequency gives a 6 ns cycle time. The 3.5 ns access time means data appears at the outputs within 3.5 ns of the clock edge — this leaves 2.5 ns of the cycle for the controller to capture the data, including board trace delay and input setup time. In a 36-bit-wide bus, each read or write cycle moves 36 bits per clock. At 166 MHz, the peak bandwidth is roughly 747 MB/s (166 MHz × 36 bits ÷ 8). The 256K depth gives 262,144 unique address locations per chip.
No official successor or pin-compatible replacement is recorded on the lifecycle notice. Quantities are lot-specific and confirmed at RFQ. The 100-LQFP package (14x20 mm body, 0.5 mm pitch) and Tape & Reel packaging match the original production format. Operating temperature is commercial grade (0°C to 70°C).