NoBL synchronous SRAM — 133 MHz, 6.5 ns access
The Infineon CY7C1357C-133AXI is a 9 Mbit synchronous SRAM organized as 512K x 18.
Where it fits — telecom line cards, baseband, industrial control
The 512K x 18 organization pairs naturally with 18-bit-wide datapaths — parity or ECC memory for packet buffers, lookup tables, and FIFO emulation in networking gear. The NoBL feature eliminates the idle cycle on bus turnarounds, so a controller can issue a read immediately after a write without a dead clock.