The CY7C1355C-133BGCT is listed as Obsolete by Infineon Technologies.
Synchronous SDR SRAM — 133 MHz, 256K x 36
Part of the NoBL™ (No Bus Latency) series, this is a synchronous SDR SRAM organized as 256K words by 36 bits, totalling 9 Mbit. The 133 MHz clock rate with a 6.5 ns access time supports pipelined read/write operations without dead cycles between reads and writes — the NoBL™ architecture eliminates the turnaround latency typical of conventional synchronous SRAM. The 36-bit word width suits applications needing wide data buses: network processors, DSP memory expansion, or graphics frame buffers where the extra bits carry parity, ECC, or tag data alongside the 32-bit payload.
Package and supply — 119-PBGA, 3.3 V
Housed in a 119-ball PBGA (14x22 mm body) — a fine-pitch BGA that requires controlled reflow profiling and post-assembly X-ray inspection. Not hand-solderable in rework without a BGA rework station and pre-bake for moisture sensitivity. The commercial temperature range (0°C to 70°C) limits deployment to indoor, temperature-controlled environments — not suitable for extended or industrial temperature grades. Supplied on Tape & Reel (TR), 13-inch reel format for automated pick-and-place assembly lines.