133 MHz synchronous SDR SRAM — 9 Mbit organized 256K x 36
The Infineon CY7C1354A-133BGC is a 9 Mbit synchronous SDR (single data rate) SRAM organized as 256K x 36, clocked at 133 MHz with a 4.2 ns access time. It is designed for high-throughput data buffering in networking, telecom, and DSP applications where deterministic read/write latency at a fixed clock rate is required — no bus-turnaround dead cycles compared to asynchronous SRAM.
4.2 ns access time — timing margin for the memory controller
The 4.2 ns access time, measured from the clock edge, sets the window the memory controller has to latch valid data on a read cycle. At 133 MHz, the 256K x 36 organization delivers 36 bits per clock cycle.
Obsolete — last-time-buy closed, surplus sourcing only
For designs already in production, this part must be sourced through independent distribution as new-old-stock or qualified surplus inventory. Any board-spin or new-design project should select a current-production synchronous SRAM in the same 119-BGA footprint with comparable 133 MHz / 4.2 ns timing.