Cypress CY7C135-25JXI, SRAM - Dual Port, Asynchronous, 32Kbit (4K x 8), 25 ns access time, Parallel interface, 4.5V~5.5V supply, -40°C~85°C, 52-PLCC (19.13x19.13), Tube.
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 4.5V ~ 5.5V |
| Memory interface | Parallel |
| Operating temperature | -40°C~85°C(TA) |
| Package | Tube |
| Technology | SRAM - Dual Port, Asynchronous |
| Access time | 25 ns |
| Memory size | 32Kbit |
| Memory format | SRAM |
| Case | 52-LCC (J-Lead) |
| Memory organization | 4K x 8 |
| Write cycle time - word, page | 25ns |
The CY7C135-25JXI is a 32Kbit asynchronous dual-port SRAM organized as 4K x 8, with a 25 ns access time. It provides two independent ports with separate address, data, and control lines, allowing two bus masters to read/write the same memory array without arbitration logic.
The 25 ns write cycle time matches the read side, so back-to-back operations are symmetric.
Yes, the CY7C135-25JXI is marked obsolete by Cypress/Infineon. No official successor is listed. The part is available through independent distribution on a quoted-to-order basis.
No official replacement part is documented in the lifecycle record. For existing BOMs, the part can be sourced through independent channels while stock lasts. A board redesign to a current dual-port SRAM family may be necessary for long-term production.
It is a 32Kbit asynchronous dual-port SRAM in a 52-PLCC package (J-lead, 19.13 x 19.13 mm), organized 4K x 8, with a 25 ns access time and parallel interface.