Infineon lists the CY7C1347G-250AXC as obsolete. This is a synchronous pipeline SRAM — 4.5 Mbit organized 128K×36 — that ran at 250 MHz with a 2.6 ns access time in a 100-TQFP package.
250 MHz pipeline — what the speed ratings drive
The 250 MHz clock frequency and 2.6 ns access time are the headline numbers. This is a synchronous pipeline SRAM — it registers the address on the clock edge and pipelines the data output through internal registers, so the access time is the delay from clock edge to valid data, not the full random-access cycle. At 250 MHz the bus can sustain back-to-back reads without dead cycles, which is what makes this part a fit for high-speed cache buffers, network packet memory, and DSP scratchpads where the controller expects data every clock.
128K×36 organization — the data-width match
The 36-bit word width (128K×36) is the key fit check. A 32-bit processor with parity or ECC can map directly — 32 data bits plus 4 parity/ECC bits in one chip. A 36-bit DSP or a 72-bit memory controller would pair two of these for a 72-bit bus. The 3.15–3.6 V supply rail is standard for this generation of high-speed SRAM; the commercial temperature range (0–70°C) limits deployment to indoor, controlled environments — not for industrial or automotive.
100-TQFP footprint — layout note
The 100-TQFP (14x20 mm) is a standard fine-pitch quad flat pack. The 0.5 mm pitch needs careful routing on the fanout — the 36 data lines plus address and control signals fill most of the pins. Decoupling should follow the layout guidelines for synchronous SRAM: a 0.1 µF ceramic per supply pin pair, placed within 2 mm of the pin, with a bulk cap on the 3.3 V rail. The package is surface-mount only.