Infineon lists the CY7C1347G-133AXI as Obsolete. For existing BOM lines, the part is sourced through independent distribution against an RFQ — quantities and pricing confirmed at quote time.
128K x 36 synchronous SRAM at 133 MHz
Organised as 128K words by 36 bits (4.5 Mbit total), this is a synchronous pipelined SRAM with a 133 MHz clock input. The 4 ns access time means the first read latency is one clock cycle, then subsequent reads pipeline at the full clock rate — the throughput is set by the bus, not the access time. The 36-bit word width maps to a 32-bit data bus plus four parity/ECC bits, common in networking and telecom line-card buffer applications where single-bit error detection is needed without a separate parity SRAM.
Industrial temp grade and 100-TQFP footprint
Supply range is 3.15 V to 3.6 V — a 3.3 V nominal rail with ±5 % tolerance covers it.