64K x 36 synchronous SRAM at 166 MHz
The Infineon CY7C1346H-166AXC is a 2Mbit synchronous SRAM organized as 64K words by 36 bits, clocked at 166 MHz with a 3.5 ns access time from the clock edge. It uses a parallel memory interface and operates from a 3.15V to 3.6V supply. The 36-bit word width suits applications needing wide data paths — think network switch buffer memories, DSP coefficient storage, or telecom line-card lookup tables where a single chip handles a full 32-bit word plus parity or ECC bits.
For BOM lines already qualified to this footprint, the supply route is the independent distribution channel — surplus inventory, last-time-buy leftovers, or broker-sourced new-old-stock. Because this is a discontinued synchronous SRAM with a specific 100-TQFP footprint and 166 MHz timing, any replacement requires a board respin or a validated second-source part with the same pinout and timing envelope. Do not assume a generic 64K x 36 SRAM will match the pipeline register configuration or the clock-to-output timing of this part.
The 166 MHz clock rate sets the data rate on the synchronous bus: one 36-bit word per clock cycle, giving a peak bandwidth of about 747 MB/s. The 3.5 ns access time is measured from the rising clock edge to data valid — this is the parameter that determines setup-and-hold margin at the receiving FPGA or ASIC. A 3.5 ns tCO at 166 MHz (6 ns period) leaves roughly 2.5 ns of remaining cycle for board trace delay, receiver setup, and clock skew. That is workable for a single-load bus with short traces, but a multi-drop topology or a heavily loaded line will eat into that margin fast.