The CY7C1051DV33-10ZSXI: Housed in a 44-TSOP II (0.400", 10.16 mm width) surface-mount package, the part presents a standard JEDEC footprint with a 0.8 mm pin pitch on the long sides — the TSOP II body is narrow enough to route on a two-layer board if the decoupling caps sit close to the supply pins. The 10 ns access time means the data bus settles within one fast-clock cycle on a 100 MHz bus — the output hold time relative to the address transition is the timing parameter to watch when interfacing with a controller that samples on the same edge.
Lifecycle reality — obsolete, sourced per RFQ
Available through independent distribution channels; quantities are lot-specific and confirmed at quote time. The 44-TSOP II footprint is shared by other asynchronous SRAMs in the same density and speed grade — a BOM review against a live cross-reference is the practical next step if a direct drop-in is needed.