10 ns asynchronous SRAM for 3.3V buses
The Infineon CY7C1041GE30-10ZSXI is a 4 Mbit asynchronous SRAM organized as 256K words by 16 bits, accessed through a parallel interface with a 10 ns access and write-cycle time. It operates from a single 3V to 3.6V supply, making it a direct fit for 3.3V processor, FPGA, and DSP memory buses where the system clock or bus cycle needs no wait-state insertion at moderate speeds.
The SRAM presents valid data on the data bus within 10 ns of address stable and chip enable asserted. The 10 ns write cycle time is symmetric, so back-to-back writes at the same rate are possible without dead cycles.
It is ROHS3 compliant.