4 Mbit asynchronous SRAM in 44-TSOP II
The Infineon CY7C1041G30-10ZSXA is a 4 Mbit asynchronous SRAM organized as 256K words by 16 bits, with a parallel interface and a 10 ns access time that also defines the write cycle time for word and page operations.
The TSOP II footprint is a standard for mid-density asynchronous SRAMs and shares the same mechanical outline as other 44-pin TSOP II memory devices in the CY7C1041 base family.
Infineon has classified the CY7C1041G30-10ZSXA as Obsolete. No official successor order code is recorded in the lifecycle data. The part is ROHS3 compliant. For BOM lines that require this exact order code, sourcing runs through independent distribution channels.
