10 ns access, 5V async SRAM in 44-TSOP II
The CY7C1021D-10ZSXI is a 1 Mbit asynchronous SRAM organized as 64K x 16 bits, with a 10 ns access time that sets the bus cycle floor for the memory controller. Operating from a 4.5V to 5.5V supply, it interfaces directly with legacy 5V logic families without level translation on the data bus. The industrial temperature range (-40°C to 85°C) covers factory-floor automation, outdoor telecom base stations, and engine-bay electronics where ambient heat exceeds commercial limits.
Package and footprint fit
Housed in a 44-TSOP II package (0.400-inch body width, 10.16 mm), the surface-mount footprint matches industry-standard asynchronous SRAM pinouts — a direct layout swap for many 5V 1 Mbit parts in the same form factor. Supplied in tray packaging, suitable for hand assembly or low-volume reflow; the write cycle time matches the read access at 10 ns, so the bus timing is symmetric for both operations.
Active lifecycle and sourcing posture
The part is quoted to order against the BOM quantity; availability and current pricing are confirmed at RFQ.