512Kbit asynchronous SRAM — 15 ns access, 5V supply
The CY7C1020BN-15ZXC: The 15 ns cycle time means the part can service back-to-back read or write requests at a 66 MHz bus rate — the access time sets the window between address valid and data valid, so a controller that samples the data bus at 15 ns after address must meet the setup hold of the downstream logic. Operating from a 4.5V to 5.5V supply, this is a legacy 5V-logic part — the I/O levels are TTL-compatible, so it interfaces directly with 5V microcontrollers and CPLDs without a level translator.