The Cypress CY7C09389V-9AXI is a 1.152 Mbit synchronous dual-port SRAM organized as 64K words by 18 bits. It gives two independent buses simultaneous access to a common memory array, with on-chip arbitration logic that resolves address and semaphore conflicts. The 9 ns access time and 67 MHz clock rate support back-to-back read/write cycles without dead cycles, which is the key advantage over asynchronous dual-port parts when both ports are running near full bus speed. The 18-bit word width (16 data bits plus two parity/flag bits) is a natural fit for 16-bit DSP or microcontroller buses that need an extra tag or interrupt line per word. The parallel interface keeps the pin count at 100, packaged in a 100-TQFP (14x14 mm) for surface-mount assembly.
The only supply channel is the independent distribution market — verified new-old-stock or surplus inventory that has already been manufactured.