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Infineon Technologies CY7C09089V-12AXC — Memory (DRAM / SRAM / Flash / EEPROM)

CY7C09089V-12AXC Infineon 512Kbit Dual-Port SRAM, 12 ns

MPNCY7C09089V-12AXC
Obsolete

Infineon CY7C09089V-12AXC, 512Kbit synchronous dual-port SRAM, 64K x 8 organization, 12 ns access time, 50 MHz clock, 3V–3.6V supply, 100-TQFP (14x14), 0°C to 70°C.

Infineon Technologies CY7C09089V-12AXC datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C09089V-12AXC specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage3V ~ 3.6V
Clock frequency50 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTray
TechnologySRAM - Dual Port, Synchronous
Access time12 ns
Memory size512Kbit
Memory formatSRAM
Case100-LQFP
Memory organization64K x 8

Product details

Synchronous dual-port SRAM for shared-memory arbitration

The Infineon CY7C09089V-12AXC is a 512Kbit synchronous dual-port SRAM organized as 64K x 8 bits, designed for systems where two independent buses need simultaneous access to a shared memory block without dead cycles.

No official replacement order code is listed by Infineon for this specific variant. A pin-compatible drop-in from the same family would need to match the 100-TQFP footprint, 3.3V supply, and synchronous dual-port interface — verify the exact ordering code suffix for temperature grade and packaging.

Frequently asked questions

Is CY7C09089V-12AXC obsolete?

Yes, Infineon lists the CY7C09089V-12AXC as Obsolete. It is no longer in production and no last-time-buy is available. Sourcing is through independent distribution and surplus inventory.

What is the replacement for CY7C09089V-12AXC?

Infineon does not list a direct official replacement for this exact ordering code. A functionally compatible part would need to be a synchronous dual-port SRAM in a 100-TQFP package with 64K x 8 organization, 12 ns access time, and 3.3V supply. Check the current Infineon dual-port SRAM family for active alternatives with the same footprint and timing.

What is the access time of CY7C09089V-12AXC?

The access time is 12 ns, measured from the rising edge of the clock to data valid on the output bus. This is the key timing parameter for bus margin analysis.

What package is CY7C09089V-12AXC?

It is supplied in a 100-pin LQFP package, also specified as a 100-TQFP with a 14x14 mm body. The -AXC suffix indicates the TQFP package and commercial temperature range.