What the 25 ns access time means for bus timing
The CY7C027V-25AI: Operating from 3V to 3.6V, it mates with 3.3V DSPs, FPGAs, and MCUs without external level translation on the parallel address/data bus.
No pin-compatible drop-in replacement is documented from Infineon — a board spin would be required to migrate to a current dual-port SRAM family.
