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Infineon Technologies CY7C0241E-15AXI — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C0241E-15AXI Dual-Port SRAM, 72Kbit, 15 ns

MPNCY7C0241E-15AXI
Obsolete

Infineon CY7C0241E-15AXI dual-port asynchronous SRAM, 72Kbit (4K x 18), 15 ns access time, parallel interface, 4.5V–5.5V supply, industrial temperature -40°C to 85°C, 100-LQFP (14x14 mm) tray.

$24.7000Ref. price · indicative, final on quote
Infineon Technologies CY7C0241E-15AXI datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C0241E-15AXI specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Supply voltage4.5V ~ 5.5V
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageTray
TechnologySRAM - Dual Port, Asynchronous
Access time15 ns
Memory size72Kbit
Memory formatSRAM
Case100-LQFP
Memory organization4K x 18
Write cycle time - word, page15ns

Product details

The 18-bit word width suits designs that need a parity bit or a separate control/status lane alongside a 16-bit data path.

The 5V supply rail is typical of legacy industrial backplanes and CPLD/FPGA interfaces that have not migrated to 3.3V or lower.

Package and footprint — 100-LQFP (14x14 mm)

Housed in a 100-lead LQFP with a 14x14 mm body (supplier device package 100-TQFP), the part is a surface-mount device. The 0.5 mm pitch requires careful routing — the 100-pin count packs a lot of signal and power pins into a moderate footprint.

Obsolete — sourcing reality for sustainment programs

Infineon (formerly Cypress) has discontinued this dual-port SRAM.

Frequently asked questions

Is CY7C0241E-15AXI obsolete?

Yes, the CY7C0241E-15AXI is marked Obsolete by Infineon. For sustainment of existing designs, the part can be sourced through surplus and broker channels.

What is the access time of CY7C0241E-15AXI?

The access time is 15 ns, and the write cycle time (word, page) is also 15 ns. This timing supports bus operation up to approximately 66 MHz without wait states, assuming the address-to-data path meets the setup and hold requirements.