64Kbit dual-port asynchronous SRAM — 55 ns access time
The CY7C024-55AXC: 64Kbit (4K x 16) dual-port asynchronous SRAM in a 100-LQFP surface-mount package. Two independent ports with separate address, data, and control lines allow simultaneous reads and writes from two bus masters.
What the 55 ns access time means for the bus
In a dual-port arbitration scenario, that timing must fit the slower of the two bus masters' memory-access windows.
