4 Mbit asynchronous SRAM – BOM-fit note
The CY62148EV30LL-45ZSXIT: This is a 4 Mbit parallel asynchronous SRAM organized as 512K x 8, with a 45 ns access time. The 45 ns cycle means the part can be read or written every 45 ns — a 22 MHz bus ceiling before wait states. Packaged in a 32-TSOP II (0.400-inch body, 10.16 mm width) — the footprint is shared across the MoBL family, so a layout for a 4 Mbit can be reused if the BOM later moves to an 8 Mbit sibling. Surface-mount only.
Active production – sourcing posture
No official successor or pin-compatible alternative is published in the same series; the MoBL family spans multiple densities (1 Mbit to 16 Mbit) with the same 32-TSOP II footprint, so a density upgrade is possible without a board spin. RoHS3 compliant (2011/65/EU + 2015/863).