45 ns access time and 2 Mbit density for moderate-speed parallel buses
The CY62136ESL-45ZSXI is a 2 Mbit asynchronous SRAM from Infineon's MoBL series, organized 128K x 16 and accessed through a parallel interface. The 45 ns access time sets the read-cycle ceiling for the bus — the processor must insert wait states if its memory controller cannot meet this window at the selected clock rate.
Housed in a 44-TSOP II (10.16 mm body width, 0.400-inch pitch), the footprint is standard for 128K x 16 asynchronous SRAMs in this density class. Surface-mount assembly with a tray shipping medium — no tape-and-reel option is listed, so pick-and-place lines should verify feeder compatibility. The write cycle time matches the read access at 45 ns (word and page mode), so the bus timing is symmetric — no separate write-recovery penalty when toggling between read and write on consecutive cycles.
ROHS3 compliant. No REACH, UL, or IEC certification is cited in the available documentation — the part carries the standard commercial RoHS declaration for the MoBL series.