Cypress CY23S08SI-4, PLL-based clock buffer / zero delay buffer, 140 MHz max, 1:8 fanout, LVCMOS/LVTTL input, LVCMOS output, 3V–3.6V supply, -40°C to 85°C, 16-SOIC.
| Parameter | Value |
|---|---|
| Type | Clock Buffer, Zero Delay Buffer |
| Mounting | Surface Mount |
| Voltage | 3V ~ 3.6V |
| Frequency | 140MHz |
| Operating temperature | -40°C ~ 85°C (TA) |
| PLL | Yes with Bypass |
| Input | LVCMOS, LVTTL |
| Output | LVCMOS |
| Package | Bulk |
| Case | 16-SOIC (0.154\", 3.90mm Width) |
| Divider (Multiplier) | Yes/No |
| Number of circuits | 1 |
| Ratio - Input:Output | 1:8 |
| Differential - Input:Output | No/No |
Runs on a 3V to 3.6V supply, which matches 3.3V logic families directly — no level translator needed for most FPGA banks, CPLDs, or clock synthesizers.
This part is RoHS non-compliant. For standard EU RoHS builds, use the RoHS-compliant variant.
Submit an RFQ for a firm delivery commitment.
No, the CY23S08SI-4 is RoHS non-compliant. It contains lead. For RoHS-compliant builds, use the CY23S08SXI-4 variant.
The difference is RoHS compliance. The CY23S08SI-4 is RoHS non-compliant (contains lead), while the CY23S08SXI-4 is the RoHS-compliant version. All other specifications — 140 MHz max frequency, 1:8 fanout, 3V–3.6V supply, -40°C to 85°C temperature range, SOIC-16 package — are identical.
The CY23S08SI-4 includes a PLL with bypass capability. The PLL cleans incoming jitter and aligns output edges to the input. Bypass mode feeds the input clock directly to the outputs without phase adjustment, useful for test or low-jitter paths.
The CY23S08SI-4 is listed as a Clock Buffer and Zero Delay Buffer. It distributes one clock input to eight outputs with minimal skew and phase alignment.