2Mbit SPI FRAM at 50 MHz — the speed-density trade-off
The CY15V102QN-50SXI: The 8 ns access time means the first byte appears on the SO line within 8 ns of the active clock edge — useful when the MCU is polling a status register in a tight loop and every cycle matters. For sequential reads, the 50 MHz clock delivers 6.25 MB/s raw throughput, enough to stream a 256-byte sector in about 41 µs.
1.8V supply, industrial temperature — board-fit constraints
The supply range is 1.71V to 1.89V — a tight 1.8V nominal rail.