12-bit SAR ADC with a parallel bus and flexible input mux
The MAX1293BEEG+ is a 12-bit successive-approximation-register (SAR) ADC that samples at 250k samples per second — fast enough to digitize a 25 kHz sine wave with Nyquist margin, but the parallel interface means the controller must be ready to grab the data word on every conversion-complete strobe. The front-end multiplexer accepts either two pseudo-differential or four single-ended inputs, selected by the channel-address bits on the parallel bus. The MUX-S/H-ADC configuration means the internal sample-and-hold captures the selected channel before conversion starts — the 1:1 S/H-to-ADC ratio keeps the aperture delay constant across all channels.
Supply rails and reference — the two decisions that set the noise floor
This split-rail architecture lets the core run at 3.3 V while the digital I/O talks directly to a 1.8 V or 2.5 V host — no external level shifter needed on the data bus. The voltage reference can be driven externally or sourced from the internal 2.5 V reference. Using the internal reference simplifies the BOM but ties the full-scale range to 2.5 V; an external reference lets you scale the input span to match the sensor output, which matters when the signal swing is only a few hundred millivolts.
Housed in a 24-QSOP (the supplier device package; the base 24-SSOP body is 0.154-inch wide, 3.90 mm), the footprint is compact enough for multi-channel boards while keeping the pin pitch at 0.0256 inch — routable on a two-layer board if the analog and digital grounds are split cleanly under the package.