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Analog Devices LTC691CSW#PBF — Power Management (PMIC / Gate Driver)

LTC691CSW#PBF Supervisor IC, 4.65V Threshold, 16-SOIC

MPNLTC691CSW#PBF
End of Life

Linear Technology LTC691CSW#PBF Simple Reset/Power-On Reset IC, Active High/Active Low Reset, Open Drain Output, 4.65V Threshold, 35ms Timeout, 16-SOIC (0.295", 7.50mm Width), Tube.

$12.24Ref. price · indicative, final on quote
Packaging16-SOIC (0.295", 7.50mm Width)
RoHSROHS3 Compliant
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LTC691CSW#PBF specifications
ParameterValue
TypeSimple Reset/Power-On Reset
MountingSurface Mount
Voltage - threshold4.65V
Number of voltages monitored1
Operating temperature0°C ~ 70°C (TA)
ResetActive High/Active Low
OutputOpen Drain or Open Collector
PackageTube
Reset timeout35ms Minimum
Case16-SOIC (0.295\", 7.50mm Width)

Product details

Supervisor IC with 4.65V threshold and 35ms timeout

The LTC691CSW#PBF is a single-channel Simple Reset/Power-On Reset supervisor in a 16-SOIC package. It monitors a single voltage rail at a 4.65V threshold and asserts a reset output for a minimum of 35ms after the rail rises above that threshold. The reset output is available as both Active High and Active Low signals, driven by an open-drain or open-collector stage. This gives the designer flexibility to interface with either active-low or active-high reset inputs on the downstream processor or FPGA without an external inverter. The 16-SOIC wide-body package (7.50mm width) provides adequate creepage for systems where the supervisor shares a board with higher-voltage rails.

Active production, ROHS3 compliant

No stock-holding claim is made here; availability is verified per inquiry.

Frequently asked questions

What is LTC691CSW#PBF's reset polarity and output type?

The LTC691CSW#PBF provides both Active High and Active Low reset signals. The output is open drain or open collector, allowing the reset lines to be wire-ORed with other supervisor outputs or pulled up to the appropriate logic voltage.

What is the reset timeout duration for LTC691CSW#PBF?

The reset timeout is a minimum of 35ms. This means the reset output remains asserted for at least 35ms after the monitored voltage rises above the 4.65V threshold, giving the system power rails and oscillator time to stabilize before the processor starts executing code.