Analog Devices DS1225AD-85+ — DC-DC Power Modules
Technical Documents PDF / CAD
RoHS Compliant · Lead-Free EIA-481 Standard
Analog Devices / DC-DC Power Modules

Analog Devices DS1225AD-85+ NVSRAM, 64Kbit, 85 ns, 28-EDIP

MPN DS1225AD-85+
End of Life Spot Stock · 24-48h Dispatch 100% Original Sealed

Analog Devices DS1225AD-85+ NVSRAM, 64Kbit (8K x 8), 85 ns access time, parallel interface, 4.5V-5.5V supply, 0°C to 70°C, 28-pin EDIP (600-mil) through-hole, ROHS3 compliant.

In Stock: 106 pcs
MOQ: 1 pcs
Logistics: DHL / FedEx DAP (Global Express · 3-7d) Russia & CIS DDP (Door-to-Door Cleared)
Dispatch: Shenzhen / HK
Unit Price (USD)
$22.12 / pc
Direct Purchase Ready
Volume Pricing Breaks Confirmed upon quotation
1+ pcs
$22.12
10+ pcs
$19.91
30+ pcs
$18.14
100+ pcs
$16.37
Working on a production BOM or have a target unit price? Submit Target Price
Buy Now

$22.12 / ea

106 in stock — maximum per order · 3–4 days lead time

$19.91 / ea from 10 pcs

Upload Full BOM List
[SPEC] Essential Parameters Snapshot Full Specifications (13)
Package / Case 28-DIP Module (0.600", 15.24mm)
Supply Voltage 4.5V ~ 5.5V
Memory / RAM 64Kbit

Full Technical Specifications

13 Parameters
DS1225AD-85+ specifications
Parameter / AttributeSpecification / Value
Memory typeNon-Volatile
MountingThrough Hole
Supply voltage4.5V ~ 5.5V
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageTube
TechnologyNVSRAM (Non-Volatile SRAM)
Access time85 ns
Memory size64Kbit
Memory formatNVSRAM
Case28-DIP Module (0.600\", 15.24mm)
Memory organization8K x 8
Write cycle time - word, page85ns
[DESK] Shenzhen Spot Allocation · 2h Response

Need Immediate Spot Stock or Shortage Allocation for DS1225AD-85+?

Factory lead times blocking production? We lock verified brand-new original stock in Shenzhen within 2 hours.

Quote SLA 2 Hours
[01] Emergency Shortage 24-48h Shenzhen Dispatch

Direct access to Shenzhen floor inventory, franchised allocation buffers, and factory bonded stock to resolve line-down shutdowns.

[02] Industrial Packaging Tape & Reel / Tray / Tube

Standard factory-sealed packaging compliant with EIA-481 standards for automated high-speed SMT pick-and-place lines.

[03] WhatsApp QC Proof 45x Microscope QC Photos

High-resolution photos of original reel labels, 2D DataMatrix, and pin coplanarity sent via WhatsApp/Telegram before you release wire payment.

● USD Wire Transfer (SWIFT T/T) · DAP Express / DDP Delivery

Technical Details & Description

NVSRAM technology — SRAM speed with battery-backed retention

The DS1225AD-85+: This is a Non-Volatile SRAM (NVSRAM) — it combines the fast read/write cycle of a standard SRAM (85 ns access time, 85 ns write cycle) with an integrated lithium energy cell that retains the memory contents when the main supply is removed. No external battery, no EEPROM write-cycle wear, and no data-loss during power transitions. The memory is organized as 8K x 8 bits (64Kbit total) with a parallel interface.

28-pin EDIP footprint — legacy through-hole, direct socket replacement

Housed in a 28-pin EDIP (600-mil wide, 0.100-inch pitch) through-hole module. The EDIP is the standard footprint for this class of NVSRAM — it drops into existing sockets on boards designed for the Dallas Semiconductor/Maxim DS1225 series. The supplier device package (28-EDIP) matches the industry-standard pinout for 8K x 8 NVSRAMs. Shipping in Tube packaging — typical for through-hole DIP modules. No tape-and-reel option; this is a manual-insertion part for through-hole assembly lines or rework benches.

ROHS3 compliant (2015/863/EU) — no lead, mercury, cadmium, or restricted phthalates. No RoHS exemption is required for this part, so it ships freely into EU-regulated markets without documentation overhead. Availability and current pricing confirmed at RFQ time.

Frequently asked questions

What is the 85 ns access time and why does it matter for my system bus?

The 85 ns access time is the maximum time the memory takes to present valid data after the address is latched. For a system with a 10 MHz bus clock (100 ns cycle), this leaves only 15 ns of timing margin after the access completes — tight but workable if the bus controller has zero-wait-state capability. A faster part (70 ns or 55 ns) would add margin, but the 85 ns variant is the standard speed grade for most legacy 8-bit microcontroller interfaces.

Does this NVSRAM require an external battery or supercapacitor?

No. The DS1225AD-85+ integrates a lithium energy cell inside the EDIP module. The memory retains data for years without external power — no coin cell, no supercapacitor, and no battery holder on the PCB. This is the defining advantage over battery-backed SRAM modules.

DS1225AD-85+
Verified Allocation
Quote