Active 5 V inverting bus transceiver in 20-TSSOP
Typical applications include memory bus buffering, backplane transceivers, and data-communication interfaces in industrial control, telecom, and computing equipment where inverting polarity is required on the data path.
The asymmetric drive — 32 mA sourcing, 64 mA sinking — is deliberate: it handles the capacitive load of a heavily loaded backplane or memory bus where the low-level edge needs more current to meet the worst-case VOL. That 64 mA sink is roughly double what the non-inverting 74ABT2245 offers on either edge, so this part is the choice when the bus has many loads or long traces. The 5 V supply rail means it mates directly with legacy 5 V TTL or CMOS logic; do not use it on a 3.3 V bus without level translation.
The 20-TSSOP body is 4.40 mm wide — a standard footprint shared with other 20-pin TSSOP transceivers, so a board layout designed for a 74ABT2245 in TSSOP-20 will accept this part if the polarity inversion is acceptable.
Lifecycle: active, no LTB pressure
The 74ABT series is mature but still supported by TI; no official successor has been announced.