The 74LS273PC is an octal D-type flip-flop with a master reset input. It clocks data on the negative edge of the clock signal, and the non-inverted outputs drive the bus directly — no external inverter needed for the polarity. At 30 MHz max clock frequency, the part handles 8-bit register or latch functions running at typical bus speeds for 5 V logic systems. The 27 ns propagation delay (at 5 V, 15 pF load) sets the timing margin for the data setup window — downstream logic must sample the output after this delay settles. Quiescent current is 27 mA — budget this into the rail's total load for a board with multiple 74LS devices.
20-pin DIP, 0.300-inch (7.62 mm) body width, through-hole mounting. The 20-PDIP supplier package code matches the standard narrow DIP footprint — 0.100-inch row spacing, 0.100-inch pin pitch. No thermal pad; no special decoupling beyond a 0.1 µF ceramic per device near the supply pins. Suitable for indoor equipment, lab instruments, or benchtop systems. Not rated for automotive or extended industrial use.