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Lattice Semiconductor Corporation LCMXO3LF-6900C-5BG256C — FPGA / CPLD & Programmable Logic

Lattice LCMXO3LF-6900C-5BG256C MachXO3 FPGA, 6864 LEs

MPNLCMXO3LF-6900C-5BG256C
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Lattice Semiconductor MachXO3 FPGA, LCMXO3LF-6900C-5BG256C, 6864 logic elements, 206 I/O, 245760 total RAM bits, 256-LFBGA package, Tray.

$22.1500Ref. price · indicative, final on quote
Packaging256-LFBGA
RoHSROHS3 Compliant
SeriesMachXO3
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LCMXO3LF-6900C-5BG256C specifications
ParameterValue
SeriesMachXO3
MountingSurface Mount
Voltage2.375V ~ 3.465V
Operating temperature0°C ~ 85°C (TJ)
PackageTray
Number of i (O)206
Case256-LFBGA
Total RAM bits245760
Number of LABs (CLBs)858
Number of logic elements (Cells)6864

Product details

Logic density and I/O — what 6864 LEs and 206 I/O mean for your BOM

The LCMXO3LF-6900C-5BG256C packs 6864 logic elements and 206 I/O in a 256-CABGA package. That density sits between a large CPLD and a small FPGA — enough to absorb a few dozen 8-bit registers, a state machine, and some glue logic without needing an external CPLD for boot or bridge functions. The 245760 total RAM bits are distributed across the fabric as block RAM, useful for small FIFOs or line buffers in video or sensor interfaces. With 858 LABs/CLBs, each containing eight LUTs and flip-flops, the architecture maps well to wide data-path muxing or address decoding.

Package and board integration — 256-CABGA footprint demands

The 256-CABGA (14x14 mm) is a 1.0 mm pitch BGA — the 0.50 mm ball pitch on the inner rows requires a 4-layer PCB minimum for fan-out. The supplier device package is 256-CABGA (14x14), so the land pattern matches the standard JEDEC MO-216 footprint. Surface-mount assembly with a standard reflow profile; no underfill is mandated for commercial temperature operation. The operating temperature range is 0°C to 85°C (TJ), which is the commercial grade; junction temperature must stay below 85°C, so the thermal vias under the BGA pad should be sized for the expected power dissipation.