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Lattice Semiconductor Corporation LCMXO3LF-1300E-5UWG36ITR1K — FPGA / CPLD & Programmable Logic

LCMXO3LF-1300E-5UWG36ITR1K Lattice MachXO3 FPGA, 1280 LUTs

MPNLCMXO3LF-1300E-5UWG36ITR1K
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Lattice Semiconductor Corporation MachXO3 FPGA, LCMXO3LF-1300E-5UWG36ITR1K, 1280 LUTs, 28 I/O, 64 Kbit RAM, 36-UFBGA WLCSP, -40°C to 100°C, Tape & Reel.

Packaging36-UFBGA, WLCSP
RoHSROHS3 Compliant
SeriesMachXO3
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LCMXO3LF-1300E-5UWG36ITR1K specifications
ParameterValue
SeriesMachXO3
MountingSurface Mount
Voltage1.14V ~ 1.26V
Operating temperature-40°C ~ 100°C (TJ)
PackageTape & Reel (TR) Cut Tape (CT)
Number of i (O)28
Case36-UFBGA, WLCSP
Total RAM bits65536
Number of LABs (CLBs)160
Number of logic elements (Cells)1280

Product details

1280 LUTs in a 2.54 x 2.59 mm WLCSP

The Lattice LCMXO3LF-1300E-5UWG36ITR1K is a MachXO3 FPGA packing 1280 logic elements (LUTs) in a 36-ball WLCSP that measures just 2.54 x 2.59 mm on the board. That die-scale footprint makes it a fit for space-constrained portable or embedded designs where a larger BGA or QFP package would not route. With 28 user I/O and 64 Kbit of embedded block RAM distributed across 160 logic-array blocks, this device handles glue-logic consolidation, I/O expansion, or control-plane sequencing without the power and latency of a larger FPGA. The core supply is a tight 1.14 V to 1.26 V — the 1.2 V nominal rail must stay within that window across load transients, or the internal PLLs and routing can lose lock.

Industrial temperature grade and active lifecycle

That range covers outdoor telecom enclosures, engine-bay-adjacent modules, and factory-floor controllers where the ambient can hit 85°C with self-heating on top. The part is ROHS3 compliant and ships in Tape & Reel — the standard format for high-volume pick-and-place assembly.

Sourcing and BOM-fit considerations

The 36-WLCSP package uses a 0.4 mm ball pitch — a standard HDI PCB stack-up with microvias can fan out all 28 I/O on two layers, but the centre balls (VCC and GND) need a via-in-pad or a buried via to avoid routing congestion. The 2.54 x 2.59 mm body means the decoupling caps sit outside the package shadow, not under it. No minimum order quantity is imposed at the quote stage.

Frequently asked questions

What is the difference between LCMXO3LF-1300E-5UWG36ITR1K and LCMXO3LF-1300E-5UWG36CTR1K?

The two parts share identical logic density (1280 LUTs), I/O count (28), package (36-WLCSP), and supply voltage. They are footprint- and function-compatible — a board designed for one can accept the other without layout changes, provided the system temperature range allows it.