32-macrocell CPLD with 10 ns pin-to-pin delay
The LC4032V-10TN48I is a 32-macrocell CPLD from Lattice's ispMACH 4000V family, offering 32 I/O pins and a propagation delay of 10 ns max. That 10 ns tpd sets the combinatorial logic ceiling — any path through the device must settle within that window, which means it handles glue logic, address decoding, or state machines running up to about 80-100 MHz in a typical synchronous design.
The footprint is the same as many other 48-pin Lattice CPLDs, so a board laid out for the 7.5 ns variant (LC4032V-75TN48I) accepts this 10 ns part without a layout change. It ships in a tray, not tape-and-reel, which is typical for this package size — the tray keeps the leads aligned during handling and reflow.
In-system programmable via JTAG — no separate programmer voltage needed; the 3.3 V supply is enough for the programming algorithm, which simplifies board-level rework and field updates.