56-QFN 7×7 — wireless SoC with integrated memory
The ESP32-S3R8 is a 56-VFQFN exposed-pad package (7×7 mm) combining a 2.4 GHz Wi-Fi 4 / BLE 5.0 radio with an MCU core and 8 MB of on-package PSRAM. With 30 GPIOs, the part supports I²C, I²S, SPI, UART, and USB serial interfaces, making it a single-chip anchor for connected products that need local sensor processing and cloud uplink on the same die.
Active production — no PCN watch needed
No second-source or pin-compatible drop-in exists from another vendor in the same 56-QFN footprint — the ESP32-S3 family is the only occupant of this package/feature intersection.
21 dBm TX power, -98.4 dBm RX sensitivity — link budget for real walls
The radio delivers 21 dBm output power at the antenna port and achieves -98.4 dBm receiver sensitivity. That gives roughly 119 dB of link budget at the 1 Mbps PHY rate — enough to punch through two interior drywall partitions at 30 m range in a typical office environment. The 150 Mbps PHY data rate (802.11n HT20) is shared between the Wi-Fi and BLE stacks; the dual-mode MAC handles time-slicing so a BLE scan does not stall the Wi-Fi TCP stream. For a product streaming sensor data over Wi-Fi while a phone app connects via BLE for commissioning, the radio handles both concurrently without an external co-processor.
8 MB PSRAM — headroom for OTA image buffers and ML inference
The 8 MB PSRAM is mapped into the CPU address space alongside the internal SRAM, so a firmware image larger than the internal RAM can execute in place from PSRAM with a small latency penalty (one extra wait state per access). A typical OTA update buffer of 1.5 MB leaves 6.5 MB for a TensorFlow Lite Micro model and its scratch buffers. The 3.3 V supply rail is shared with the radio PA — a linear regulator with 200 mV dropout margin is sufficient if the input rail stays above 3.5 V under load.