SiP memory ceiling and the application stack budget
The ESP32-PICO-V3-ZERO: The 520 KB on-chip SRAM is the practical limit for the application stack plus the Wi-Fi/BLE protocol buffers — a bare-metal sensor node logging a few hundred bytes per second leaves ~300 KB free after the RTOS and networking layers; an OTA-capable firmware image that decompresses into RAM will eat into that headroom fast. 448 kB ROM holds the bootloader and core library routines, not application code — the flash is external via the SPI interface, so the board-level SPI flash part number determines the total non-volatile storage budget.
At 19.5 dBm conducted output power and a PCB trace antenna, the EIRP is antenna-gain-limited — expect 15–17 dBm effective isotropic radiated power from the on-board trace, which delivers roughly 50–80 m range in an open office with the receiver at -97 dBm sensitivity. The -97 dBm sensitivity floor is the DSSS 1 Mbps rate; at 150 Mbps the sensitivity drops to around -75 dBm — the actual link margin is set by the chosen PHY rate, not the headline sensitivity figure.
Active lifecycle and compliance posture
The module carries the industrial temperature grade of -40 to 85 °C, covering outdoor enclosures, engine-bay-adjacent telematics, and unconditioned factory-floor edge nodes without derating.