36 macrocells, 10 ns — the speed-grade decision
The AMD XC9536XL-10VQG64C is a 36-macrocell CPLD from the XC9500XL series, with a maximum pin-to-pin delay of 10 ns. That 10 ns tpd sets the combinatorial logic path ceiling — registered inputs and registered outputs bypass it, but any signal that fans out through the switch matrix and back to a pin before the clock edge must fit inside that window. In-system programmable with a minimum of 10,000 program/erase cycles, it suits firmware-updateable glue logic in production — no socket or external programmer needed once the board is assembled.
Supply and temperature — 3.3 V commercial
The 64-TQFP package (supplier device package 64-VQFP, 10x10 mm body) provides 36 user I/O. The 0.5 mm pitch demands a controlled-impedance stack-up if any I/O runs at the rated 10 ns edge rate; a 2-layer board can fan out the inner rows with via stitching to the ground plane.
The base product number XC9536 identifies the family; the -10 suffix denotes the 10 ns speed grade, and the VQG64 suffix specifies the 64-VQFP package in tray format. A BOM line coded for the base number alone must specify the full order code to lock the speed and package variant.