Texas Instruments TPS70145PWP — Power Management (PMIC / Gate Driver)
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Texas Instruments / Power Management (PMIC / Gate Driver)

TPS70145PWP Texas Instruments Dual LDO, 3.3V/1.2V

MPN TPS70145PWP
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Texas Instruments TPS70145PWP dual-output LDO, 20-PowerTSSOP, fixed 3.3V/1.2V outputs, 500mA/250mA, 60dB PSRR at 1kHz, -40°C to 125°C, active.

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[SPEC] Essential Parameters Snapshot Full Specifications (16)
Package / Case 20-PowerTSSOP (0.173", 4.40mm Width)

Full Technical Specifications

16 Parameters
TPS70145PWP specifications
Parameter / AttributeSpecification / Value
Output typeFixed
MountingSurface Mount
Voltage - input6V
Voltage dropout0.28V @ 500mA, -
Voltage - output (Min (Fixed))3.3V, 1.2V
Output current500mA, 250mA
Current - supply230 µA
Current - quiescent190 µA
Operating temperature-40°C ~ 125°C
PSRR60dB (1kHz)
PackageTube
Case20-PowerTSSOP (0.173\", 4.40mm Width)
Control featuresEnable, Power Good, Reset, Sequencing
Protection featuresOver Current, Over Temperature, Reverse Polarity, Under Voltage Lockout (UVLO)
Number of regulators2
Output configurationPositive
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Technical Details & Description

Dual-rail sequencing for mixed-signal power

The TPS70145PWP is a dual-output low-dropout regulator from Texas Instruments, delivering fixed 3.3 V and 1.2 V rails in a 20-lead HTSSOP package. The main output is rated for 500 mA, the secondary for 250 mA, making it a natural fit for powering the analog and digital core supplies on a mixed-signal board where the ADC or DAC runs from 3.3 V and the FPGA or MCU core from 1.2 V. The 60 dB PSRR at 1 kHz means the output rejects switching noise from a downstream DC-DC converter by a factor of 1000 — critical when the 3.3 V rail also feeds a precision reference or a sensor front-end. Below 1 kHz the rejection is higher; above it the PSRR rolls off, so the upstream filter inductor and the output capacitor's ESR matter more for high-frequency ripple.

Protection set and operating range

The regulator includes overcurrent, overtemperature, reverse polarity, and undervoltage lockout (UVLO) protection. The UVLO threshold keeps the outputs off until the input rail is stable above the dropout region, preventing the 1.2 V core from browning out during a slow power-up ramp. The quiescent current is 190 µA typical, rising to 230 µA maximum under full supply — low enough that the regulator's own draw does not dominate the system budget in a battery-backed design. With a 5 V input, that leaves 1.42 V of headroom — plenty for the internal pass element to stay in the linear region across temperature.

Package and thermal interface

The 20-PowerTSSOP (HTSSOP) package has an exposed thermal pad on the bottom. The supplier device package is 20-HTSSOP, which is the same footprint with the pad. Control features include enable pins, a power-good flag, reset output, and sequencing logic. The sequencing allows the 3.3 V rail to come up before the 1.2 V rail, or vice versa, depending on the external resistor divider — a common requirement for FPGA power-on sequences.

Texas Instruments lists no official pin-compatible second source for this part. The dual-output fixed-voltage combination and the sequencing logic are specific to the TPS701xx family; a parametric substitute would need to match the 3.3 V/1.2 V fixed outputs, the 500 mA/250 mA current split, and the HTSSOP-20 footprint.

Frequently asked questions

What is the PSRR of the TPS70145PWP and why does it matter?

The PSRR is 60 dB at 1 kHz. This means the output rejects conducted noise from the input rail by 1000:1 at that frequency.

What protection features does the TPS70145PWP include?

The regulator integrates overcurrent, overtemperature, reverse polarity, and undervoltage lockout (UVLO) protection. The UVLO prevents the outputs from turning on until the input voltage exceeds the dropout threshold, which protects downstream logic from operating in the brownout region.

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