Dual 10-bit DAC with SPI — what the settling time means for your update rate
The TLV5617AIDR packs two 10-bit voltage-output DACs in an 8-pin SOIC, communicating over an SPI bus. Each channel settles to within ±0.5 LSB in 10 µs — that sets the per-channel update ceiling at 100 kSPS when you alternate writes, or 50 kSPS per channel if both update simultaneously. The string-architecture core delivers inherent monotonicity: DNL is ±0.1 LSB typical, INL ±0.7 LSB.
Supply rails and board integration
No separate AVDD/DVDD sequencing needed. The external reference input lets you set the output span independently of the supply voltage.