Hex inverter with unbuffered outputs
The SN74LVU04APWT is a Texas Instruments hex inverter from the 74LVU family, containing six independent inverter gates in a single 14-TSSOP package. Each gate has a single input and provides the inverted logic level at the output, with unbuffered (inverting-only) topology that gives a cleaner propagation path than buffered alternatives in some oscillator or pulse-shaping circuits.
2V to 5.5V supply, 7ns propagation delay
Operating from 2V to 5.5V, this inverter covers the full 3.3V and 5V logic rails common in mixed-voltage designs. The 7ns max propagation delay at 5V with a 50pF load sets the timing budget for the signal path — at 3.3V the delay increases, so the actual toggle rate at the receiver will be lower than the bare 7ns figure suggests. Output drive is rated 12mA source and 12mA sink at the rated supply voltage, enough to drive a handful of CMOS inputs or a low-power LED indicator without a separate buffer. The 20µA max quiescent current keeps the static power draw negligible in battery-powered or always-on sections. Input logic thresholds are 0.3V low and 1.7V high at 5V supply — the 1.4V hysteresis gap provides noise immunity on slow-rising edges.
Board-fit and supply integration
Surface-mount to a 14-TSSOP land pattern — the 0.65mm pitch requires standard SMT assembly capability but does not demand fine-pitch inspection. Supply bypass: a 0.1µF ceramic capacitor placed within 5mm of each VCC pin (pins 7 and 14) is sufficient for the 20µA quiescent draw, though the 12mA output transients benefit from a 1µF bulk cap per four gates. The unbuffered output topology means the part can be used in crystal oscillator feedback paths where a standard Schmitt-trigger inverter would add unwanted hysteresis.