Open-drain inverter for level translation and wired-OR
The SN74AUP1G06DCKT is a single inverter from TI's 74AUP ultra-low-power logic family, but with an open-drain output stage instead of the standard push-pull. This means the output can sink current to ground but cannot source it — the pull-up resistor is external, tied to whatever voltage the downstream logic needs. Quiescent current maxes at 500 nA — the defining spec for always-on sense circuits, wake-up logic, and interrupt collectors that must not drain the battery during sleep.
Output drive and timing budget
The open-drain output sinks 4 mA at a low logic level — enough to drive a standard CMOS input or an optocoupler LED directly. There is no high-level output current because the output never drives high; the external pull-up resistor handles the rise time. Propagation delay is 10.5 ns max at 3.3 V with a 30 pF load, which sets the timing floor for a single-gate buffer stage in a clock or reset path. Input logic thresholds are specified as 0.1 V to 0.45 V for low and 3.6 V for high — the wide low-level window means the gate reliably interprets a weak pull-down as a logic 0, useful when the driving source has limited sink capability.
Housed in a 5-pin SC-70-5 (SOT-353) package, the SN74AUP1G06DCKT occupies roughly 2.0 mm × 2.1 mm on the board — a single-gate footprint that fits into tight sensor modules or multi-layer phone-style PCBs.