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Texas Instruments SN74AHC240PWR — Memory (DRAM / SRAM / Flash / EEPROM)

SN74AHC240PWR TI 74AHC Buffer Inverting 3-State 20-TSSOP

MPNSN74AHC240PWR
End of Life

Texas Instruments 74AHC Buffer Inverting, SN74AHC240PWR, 20-TSSOP, 2 V to 5.5 V supply, 8 mA output, 3-State, -40°C to +85°C.

$0.56Ref. price · indicative, final on quote
Packaging20-TSSOP (0.173", 4.40mm Width)
RoHSROHS3 Compliant
Series74AHC
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

SN74AHC240PWR specifications
ParameterValue
Series74AHC
Logic typeBuffer, Inverting
Output type3-State
MountingSurface Mount
Supply voltage2V ~ 5.5V
Current - output high, low8mA, 8mA
Operating temperature-40°C ~ 85°C (TA)
PackageTape & Reel (TR); Cut Tape (CT)
Case20-TSSOP (0.173\", 4.40mm Width)
Number of elements2
Number of bits per element4

Product details

Octal inverting buffer with 3-state bus hold

The SN74AHC240PWR is a dual 4-bit inverting buffer from Texas Instruments' 74AHC family, packing eight channels of 3-state output into a 20-pin TSSOP. It operates across a 2 V to 5.5 V supply range, making it a direct drop-in for mixed-voltage logic buses where the core runs at 3.3 V but the peripheral bus needs 5 V tolerance on the input side.

Supply range and output drive at the board level

With 8 mA source and sink capability per channel, this buffer handles standard CMOS and TTL fan-out for a typical load of four to six downstream inputs without external line drivers. The 3-state outputs let multiple devices share a common data bus — the high-impedance state isolates the buffer when another device drives the line, which is the standard bus-sharing arrangement on a memory or peripheral backplane. The -40 °C to +85 °C industrial temperature grade covers most factory-floor and outdoor telecom enclosures; the timing margins at the cold corner are tighter than at room temperature, so a design targeting 85 °C ambient should verify the propagation delay at the hot corner against the setup-time requirement of the receiving flip-flop.