Quad LVDS receiver with 50 mV hysteresis margin
The SN65LVDS348PW is a quad-channel LVDS receiver from the 65LVDS family, accepting four differential inputs and presenting four single-ended LVTTL/LVCMOS outputs. Each channel operates up to 560 Mbps, with a 50 mV input hysteresis that provides noise immunity on long backplane or cable runs where common-mode shifts and reflections degrade signal integrity.
16-TSSOP footprint and board integration
Housed in a 16-lead TSSOP with 0.65 mm pitch and 4.40 mm body width. The narrow pitch demands a controlled-impedance trace layout for the LVDS inputs — route the differential pairs with 100 Ω differential impedance and keep the pair length mismatch under 5 mm to preserve the 560 Mbps eye opening. The supply decoupling should use a 0.1 µF ceramic within 2 mm of each VCC pin.