8-to-1 camera serializer for short-reach LVDS links
The SN65LVDS315RGET is a serializer that converts 8 parallel CMOS inputs into a single LVDS serial stream at up to 201 Mbps. This 8:1 reduction cuts the ribbon cable or FPC width between a camera module and the processor from 8 data lanes to one differential pair, saving board area and connector cost in compact imaging systems. It operates from a 1.65 V to 1.95 V core supply, matching the 1.8 V rail common in mobile and embedded camera designs.
Data rate and serialization margin
The 201 Mbps serial data rate corresponds to a 25.125 MHz pixel clock for an 8-bit parallel bus. At this rate the LVDS output swing and skew are well within the receiver's eye-opening budget over a 0.5-meter twisted-pair or FPC link. The 8:1 ratio means the parallel input side clocks at one-eighth the serial rate, relaxing the FPGA or ISP timing constraints on the camera interface. Inputs are CMOS-level with no internal termination — the source impedance of the driving camera sensor or bridge chip sets the signal integrity. The single LVDS output is a current-mode differential pair; a 100-ohm termination resistor at the deserializer input completes the path.
Package and board integration
The 24-VQFN (4x4) supplier package footprint matches the standard QFN-24 land pattern. Available in Tape & Reel (TR) or Cut Tape (CT) for prototyping. The CT option allows low-quantity builds without committing to a full reel.