LVDS fan-out and signal routing
The SN65LVDS22PW is a 1 x 2:2 LVDS buffer and multiplexer from Texas Instruments, routing a single differential input to one of two LVDS output pairs. It operates at data rates up to 250 Mbps with a propagation delay of 4.0 ns, making it suitable for clock distribution or data fan-out in backplane and cable interconnect applications where signal integrity over distance matters.
Supply and timing budget
The 4.0 ns propagation delay sets the timing margin for the downstream receiver; in a 250 Mbps link with a 4 ns unit interval, the delay consumes one full bit period, which must be accounted for in the system timing budget.
Input loading and temperature range
Input capacitance is 3 pF per LVDS input pin — light enough that a string of several receivers on the same differential pair does not degrade the signal edge beyond the receiver threshold.