1:4 LVDS fanout at 400 Mbps
The SN65LVDS105PW is a single-channel LVDS buffer and multiplexer that takes an LVTTL input and delivers a 1:4 LVDS fanout. The 400 Mbps maximum data rate and 2.2 ns propagation delay define the timing budget for the downstream receivers — the 3 pF input capacitance loads the upstream driver, so the source must be able to drive that capacitance at the target edge rate.
Package and board integration
Housed in a 16-TSSOP package (4.40 mm width, 0.173" body) with a 0.65 mm pitch. The supplier device package is 16-TSSOP.