PLL Multi-Clock Generator — 36.87 MHz ceiling, 20-SSOP
No official successor or direct pin-compatible replacement is listed on the manufacturer's record. New-production requirements will need a functionally equivalent PLL clock generator in a similar package; existing BOM lines must be sourced through the independent surplus and broker channel.
The 1:6 input-to-output ratio lets a single TTL reference drive six CMOS clock loads, reducing the external fanout buffer count. Housed in a 20-SSOP (5.30 mm body width) surface-mount package, the footprint is compact enough for dense telecom line cards or industrial controller boards, but the 0.65 mm pitch demands careful board routing to maintain signal integrity on the six output traces.