Three jobs, one 64-pin package
It accepts HCSL, LVCMOS, LVDS, LVPECL, or crystal inputs and delivers CML, LVCMOS, LVDS, or LVPECL outputs across a 3:16 fanout from a single PLL core.
Output frequency ceiling — three rails
The maximum output frequency is specified at three tiers: 200 MHz, 1 GHz, and 3 GHz, depending on the output format and divider path selected. That 3 GHz top end puts this part in the range for 100G/400G line-card reference clocks or high-speed ADC/DAC sampling clocks where the jitter floor matters more than the raw frequency.
Package and mounting — 64-VFQFN with exposed pad
Housed in a 64-VFQFN exposed-pad package (9x9 mm body), surface-mount only.