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Texas Instruments LMK00301SQ/NOPB — Clock & Timing ICs

LMK00301SQ/NOPB Clock Fanout Buffer, 3.1 GHz, 48-WQFN

MPNLMK00301SQ/NOPB
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Texas Instruments LMK00301SQ/NOPB, 3:10 fanout buffer / multiplexer / translator, 3.1 GHz max frequency, CML/HCSL/HSTL/LVDS/LVPECL/SSTL/crystal inputs, HCSL/LVCMOS/LVDS/LVPECL outputs, 3.15V–3.45V supply, -40°C to 85°C, 48-WQFN exposed pad.

$12.5700Ref. price · indicative, final on quote
Packaging48-WFQFN Exposed Pad
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LMK00301SQ/NOPB specifications
ParameterValue
TypeFanout Buffer (Distribution), Multiplexer, Translator
MountingSurface Mount
Voltage3.15V ~ 3.45V
Frequency3.1 GHz
Operating temperature-40°C~85°C
InputCML, HCSL, HSTL, LVDS, LVPECL, SSTL, Crystal
OutputHCSL, LVCMOS, LVDS, LVPECL
PackageTape & Reel (TR); Cut Tape (CT)
Case48-WFQFN Exposed Pad
Number of circuits1
Ratio - Input:Output3:11
Differential - Input:OutputYes/Yes

Product details

3.1 GHz fanout buffer — universal clock translation in one package

The Texas Instruments LMK00301SQ/NOPB is a 3:10 fanout buffer, multiplexer, and level translator that handles the widest set of differential clock standards on the input side — CML, HCSL, HSTL, LVDS, LVPECL, SSTL, and even a crystal — and outputs HCSL, LVCMOS, LVDS, or LVPECL. That means a single device can replace a rack of dedicated translators on a multi-protocol clock tree, whether you're distributing a 100 MHz reference to ten FPGA banks or a 3.1 GHz SerDes clock to multiple transceivers. The 3:11 input-to-output ratio gives three selectable input muxes feeding ten outputs (the datasheet counts it as 3:10 in the description), which is enough to fan out a master clock to every PLL and SerDes on a dense board without adding external dividers or redrivers.

3.15V–3.45V supply — plan the rail

The supply range is 3.15V to 3.45V, which is a ±4.5% window around a nominal 3.3V rail. That's tighter than the ±10% many logic parts tolerate, so the 3.3V rail feeding this buffer needs a regulator with good load regulation — a standard 3.3V LDO with 1% accuracy is fine, but don't try to run it off a 3.0V or 3.6V rail without checking the margin. The device draws its current from this single rail; there's no separate core or I/O supply.

The 7x7 mm 48-WQFN with exposed pad is a standard QFN package, but the thermal pad underneath is the main heat path — and the main rework challenge. The exposed paddle needs a via-stitched thermal land on the PCB; without it, the junction temperature climbs fast above 400 mA continuous output drive.

The base product number is LMK00301, so any future variants (different package or temperature grade) would carry that prefix.

If you're dual-sourcing for supply resilience, the closest functional peer is the CDCLVP1204RGTR, but note that part tops out at 2.0 GHz and only outputs LVPECL, so it's not a pin-for-pin drop-in; the LMK00301's wider frequency range and multi-standard output flexibility are the differentiators for a high-speed mixed-signal clock tree.

Frequently asked questions

What is the maximum frequency of LMK00301SQ/NOPB?

The maximum frequency is 3.1 GHz. That covers the fastest common reference clocks — PCIe Gen5/6, 100G/400G Ethernet, JESD204B, and 64B/66B SerDes — without needing a separate high-speed redriver.

What input and output signal types does LMK00301SQ/NOPB support?

The inputs accept CML, HCSL, HSTL, LVDS, LVPECL, SSTL, and crystal. The outputs can be configured as HCSL, LVCMOS, LVDS, or LVPECL. This makes it a universal translator that can bridge between different logic families on a mixed-signal board.

Is there a direct replacement or equivalent for LMK00301SQ/NOPB?

The closest functional equivalent is the CDCLVP1204RGTR, but it's not a pin-for-pin drop-in. The CDCLVP1204 tops out at 2.0 GHz and outputs LVPECL only, whereas the LMK00301 goes to 3.1 GHz and outputs HCSL, LVCMOS, LVDS, or LVPECL. For a 1:1 replacement, stick with the LMK00301 family.