Schmitt-trigger noise margin for dirty signal lines
The CD74HCT132M96 is a quad 2-input NAND gate from the 74HCT series, but the key differentiator is the Schmitt-trigger input stage on all four gates. HCT inputs are TTL-compatible — the low threshold sits at 0.5V to 0.6V and the high threshold at 1.9V to 2.1V, giving roughly 1.3V of hysteresis. That hysteresis rejects slow edges and noise on the input lines that a standard HCT gate would toggle on. For a 5V rail, the propagation delay is 33ns into a 50pF load — fast enough for most 8-bit bus handshakes and control logic running below 15 MHz. Quiescent current maxes at 2 µA — negligible in a battery-backed system where the gate sits idle between wake events.
Supply rail and output drive
That means the part is not a candidate for a 3.3V mixed-voltage bus unless a level translator sits ahead of it. Each output can source or sink 4 mA, which drives a single LSTTL load or a CMOS input on the same 5V rail, but not a long backplane trace or a relay coil without a buffer.
Housed in a 14-SOIC package with a 3.90mm body width and 1.27mm pin pitch. The footprint is standard — the same land pattern used for a 74HC00 or 74HCT00 in the same package.