Timing and drive at the 14-SOIC footprint
The CD74HC11MT: Maximum propagation delay is 17ns at 6V with a 50pF load — this sets the data-rate ceiling for the downstream flip-flop or counter. The 5.2mA output drive is symmetric for high and low states, so rise and fall times match within the same load; no need to skew the input timing. Quiescent current sits at 2µA max, negligible for a gate that spends most of its life static.
Package and compliance
14-SOIC wide-body (0.154", 3.90mm) — standard JEDEC footprint, reworkable with hot air without bottom-side preheat. The supplier device package is 14-SOIC; the reel format (TR) suits pick-and-place at 8mm tape pitch. ROHS3 compliant — no exemption conflicts for EU or UKCA markets.