Quad 2-input AND gate in 14-SOIC
The CD74HC08M: It integrates four independent AND gates, each with two inputs, on a single IC.
2 µA quiescent, 5.2 mA output drive
Quiescent current is a maximum of 2 µA, keeping the static power draw negligible in battery-operated or power-sensitive designs. Each output can source or sink 5.2 mA (symmetrical drive), which is typical for the HC family and sufficient for driving standard CMOS logic inputs or low-current loads directly. Propagation delay is 15 ns maximum at 6V supply with a 50 pF load, setting the timing budget for the signal path at the upper supply rail.
Input logic thresholds track the supply rail
Low-level input threshold ranges from 0.5V to 1.8V, and high-level input threshold ranges from 1.5V to 4.2V, both scaled to the supply voltage — the gate interprets a 0.5V signal as a logic low across the full 2V-6V range. These rail-ratioed thresholds mean the CD74HC08M interfaces cleanly with other 74HC, HCT, or LVCMOS logic families operating at the same supply voltage without additional level translation.